#set_property INTERNAL_VREF 1.8 [get_iobanks 35]
#set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii3_txdo[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii3_txdo[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii2_txdo[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii2_txdo[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii1_txdo[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii1_txdo[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii3_rxdi[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii3_rxdi[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii2_rxdi[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii2_rxdi[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii1_rxdi[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii1_rxdi[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_rxdi[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_rxdi[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_rxdi[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_rxdi[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_rxdi[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_rxdi[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_rxdi[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_rxdi[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_rxdi[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_rxdi[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_rxdi[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_rxdi[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_rxdi[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_rxdi[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_rxdi[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_rxdi[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii0_rxctrli]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii0_rxclki]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii1_rxctrli]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii1_rxclki]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii2_rxctrli]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii2_rxclki]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii3_rxctrli]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii3_rxclki]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_txdo[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_txdo[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_txdo[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii0_txdo[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_txdo[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_txdo[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_txdo[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii1_txdo[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_txdo[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_txdo[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_txdo[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii2_txdo[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_txdo[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_txdo[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_txdo[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii3_txdo[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii0_txctrlo]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii0_txclko]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii1_txctrlo]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii1_txclko]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii2_txctrlo]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii2_txclko]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii3_txctrlo]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii3_txclko]


set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_ni[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_no[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_po[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {aledo[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {aledo[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk2m_74o]
set_property IOSTANDARD LVCMOS33 [get_ports fs8k_74o]
set_property IOSTANDARD LVCMOS33 [get_ports e1asd_74o]
set_property IOSTANDARD LVCMOS33 [get_ports {opt_warni[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {opt_warni[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii0_rxdi[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii0_rxdi[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii0_txdo[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii0_txdo[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {e1_pi[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk65mi]
set_property IOSTANDARD LVCMOS33 [get_ports clk125m_syni]
set_property IOSTANDARD LVCMOS33 [get_ports rmii0_txeno]
set_property IOSTANDARD LVCMOS33 [get_ports rmii0_rxdvi]
set_property IOSTANDARD LVCMOS33 [get_ports rmii1_rxdvi]
set_property IOSTANDARD LVCMOS33 [get_ports rmii2_rxdvi]
set_property IOSTANDARD LVCMOS33 [get_ports rmii1_txeno]
set_property IOSTANDARD LVCMOS33 [get_ports rmii2_txeno]
set_property IOSTANDARD LVCMOS33 [get_ports rmii3_rxdvi]
set_property IOSTANDARD LVCMOS33 [get_ports rmii3_txeno]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_clko[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_clko[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_reseto[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_reseto[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_reseto[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {rmii_reseto[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports ge_a_reseto]
set_property IOSTANDARD LVCMOS33 [get_ports ge_b_reseto]
set_property IOSTANDARD LVCMOS33 [get_ports spi_clki]
set_property IOSTANDARD LVCMOS33 [get_ports spi_csi]
set_property IOSTANDARD LVCMOS33 [get_ports spi_miso]
set_property IOSTANDARD LVCMOS33 [get_ports spi_mosi]
set_property IOSTANDARD LVCMOS33 [get_ports stbus_synco]
set_property IOSTANDARD LVCMOS33 [get_ports stbus_do]
set_property IOSTANDARD LVCMOS33 [get_ports stbus_di]
set_property IOSTANDARD LVCMOS33 [get_ports stbus_clko]
set_property IOSTANDARD LVCMOS33 [get_ports stbus_sigi]
set_property IOSTANDARD LVCMOS33 [get_ports stbus_sigo]
set_property IOSTANDARD LVCMOS33 [get_ports spi_intno]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rstni]
set_property IOSTANDARD LVCMOS33 [get_ports skio]
set_property IOSTANDARD LVCMOS33 [get_ports {urxdi[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {utxdo[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {urxdi[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {utxdo[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {also[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {also[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {swi[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {swi[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {swi[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {swi[2]}]
set_property PACKAGE_PIN K14 [get_ports sys_rstni]
set_property PACKAGE_PIN J21 [get_ports clk65mi]
set_property PACKAGE_PIN E6 [get_ports ref_clk125m_ni]
set_property PACKAGE_PIN F6 [get_ports ref_clk125m_pi]
set_property PACKAGE_PIN C18 [get_ports clk125m_syni]
set_property PACKAGE_PIN T21 [get_ports {also[1]}]
set_property PACKAGE_PIN E13 [get_ports {also[0]}]
set_property PACKAGE_PIN Y19 [get_ports skio]

#GSCLK
set_property PACKAGE_PIN V20 [get_ports clk2m_74o]
#GSFSP
set_property PACKAGE_PIN W22 [get_ports fs8k_74o]
#GSDAT
set_property PACKAGE_PIN W21 [get_ports e1asd_74o]
#ALMAO
set_property PACKAGE_PIN F14 [get_ports {aledo[0]}]
#ALMBO
set_property PACKAGE_PIN E14 [get_ports {aledo[1]}]


set_property PACKAGE_PIN A10 [get_ports {opt_inni[0]}]
set_property PACKAGE_PIN B10 [get_ports {opt_inpi[0]}]
set_property PACKAGE_PIN A6 [get_ports {opt_outno[0]}]
set_property PACKAGE_PIN B6 [get_ports {opt_outpo[0]}]
set_property PACKAGE_PIN A13 [get_ports {opt_warni[0]}]
set_property PACKAGE_PIN A8 [get_ports {opt_inni[1]}]
set_property PACKAGE_PIN B8 [get_ports {opt_inpi[1]}]
set_property PACKAGE_PIN A4 [get_ports {opt_outno[1]}]
set_property PACKAGE_PIN B4 [get_ports {opt_outpo[1]}]
set_property PACKAGE_PIN B13 [get_ports {opt_warni[1]}]

set_property PACKAGE_PIN J22 [get_ports spi_clki]
set_property PACKAGE_PIN H22 [get_ports spi_csi]
set_property PACKAGE_PIN H20 [get_ports spi_mosi]
set_property PACKAGE_PIN G22 [get_ports spi_miso]
set_property PACKAGE_PIN K22 [get_ports spi_intno]

set_property PACKAGE_PIN F21 [get_ports {rmii_reseto[0]}]
set_property PACKAGE_PIN D20 [get_ports {rmii_reseto[1]}]
set_property PACKAGE_PIN B17 [get_ports {rmii_reseto[2]}]
set_property PACKAGE_PIN A14 [get_ports {rmii_reseto[3]}]
set_property PACKAGE_PIN D22 [get_ports {rmii_clko[0]}]
set_property PACKAGE_PIN A20 [get_ports {rmii_clko[1]}]
set_property PACKAGE_PIN G21 [get_ports rmii0_rxdvi]
set_property PACKAGE_PIN E22 [get_ports {rmii0_rxdi[0]}]
set_property PACKAGE_PIN E21 [get_ports {rmii0_rxdi[1]}]
set_property PACKAGE_PIN B22 [get_ports rmii0_txeno]
set_property PACKAGE_PIN D21 [get_ports {rmii0_txdo[0]}]
set_property PACKAGE_PIN C22 [get_ports {rmii0_txdo[1]}]
set_property PACKAGE_PIN F20 [get_ports rmii1_rxdvi]
set_property PACKAGE_PIN E19 [get_ports {rmii1_rxdi[0]}]
set_property PACKAGE_PIN C20 [get_ports {rmii1_rxdi[1]}]
set_property PACKAGE_PIN B20 [get_ports rmii1_txeno]
set_property PACKAGE_PIN B21 [get_ports {rmii1_txdo[0]}]
set_property PACKAGE_PIN A21 [get_ports {rmii1_txdo[1]}]
set_property PACKAGE_PIN C19 [get_ports rmii2_rxdvi]
set_property PACKAGE_PIN D19 [get_ports {rmii2_rxdi[0]}]
set_property PACKAGE_PIN B18 [get_ports {rmii2_rxdi[1]}]
set_property PACKAGE_PIN B16 [get_ports rmii2_txeno]
set_property PACKAGE_PIN A19 [get_ports {rmii2_txdo[0]}]
set_property PACKAGE_PIN A18 [get_ports {rmii2_txdo[1]}]
set_property PACKAGE_PIN D14 [get_ports rmii3_rxdvi]
set_property PACKAGE_PIN C15 [get_ports {rmii3_rxdi[0]}]
set_property PACKAGE_PIN C14 [get_ports {rmii3_rxdi[1]}]
set_property PACKAGE_PIN A15 [get_ports rmii3_txeno]
set_property PACKAGE_PIN A16 [get_ports {rmii3_txdo[0]}]
set_property PACKAGE_PIN B15 [get_ports {rmii3_txdo[1]}]

set_property PACKAGE_PIN F13 [get_ports ge_a_reseto]
set_property PACKAGE_PIN D15 [get_ports ge_b_reseto]

set_property PACKAGE_PIN E2 [get_ports rgmii0_rxctrli]
set_property PACKAGE_PIN E1 [get_ports {rgmii0_rxdi[0]}]
set_property PACKAGE_PIN F1 [get_ports {rgmii0_rxdi[1]}]
set_property PACKAGE_PIN F3 [get_ports {rgmii0_rxdi[2]}]
set_property PACKAGE_PIN C2 [get_ports rgmii0_txctrlo]
set_property PACKAGE_PIN D1 [get_ports rgmii0_txclko]
set_property PACKAGE_PIN B1 [get_ports {rgmii0_txdo[0]}]
set_property PACKAGE_PIN A1 [get_ports {rgmii0_txdo[1]}]
set_property PACKAGE_PIN B2 [get_ports {rgmii0_txdo[2]}]

set_property PACKAGE_PIN K2 [get_ports rgmii1_rxctrli]
set_property PACKAGE_PIN L1 [get_ports {rgmii1_rxdi[0]}]
set_property PACKAGE_PIN M3 [get_ports {rgmii1_rxdi[1]}]
set_property PACKAGE_PIN M1 [get_ports {rgmii1_rxdi[2]}]
set_property PACKAGE_PIN M2 [get_ports {rgmii1_rxdi[3]}]
set_property PACKAGE_PIN J1 [get_ports rgmii1_txctrlo]
set_property PACKAGE_PIN J2 [get_ports rgmii1_txclko]
set_property PACKAGE_PIN H2 [get_ports {rgmii1_txdo[0]}]
set_property PACKAGE_PIN G2 [get_ports {rgmii1_txdo[1]}]
set_property PACKAGE_PIN H3 [get_ports {rgmii1_txdo[2]}]
set_property PACKAGE_PIN G3 [get_ports {rgmii1_txdo[3]}]

set_property PACKAGE_PIN W1 [get_ports rgmii2_rxctrli]
set_property PACKAGE_PIN W2 [get_ports {rgmii2_rxdi[0]}]
set_property PACKAGE_PIN Y1 [get_ports {rgmii2_rxdi[1]}]
set_property PACKAGE_PIN Y2 [get_ports {rgmii2_rxdi[2]}]
set_property PACKAGE_PIN AA1 [get_ports {rgmii2_rxdi[3]}]
set_property PACKAGE_PIN U2 [get_ports rgmii2_txctrlo]
set_property PACKAGE_PIN U1 [get_ports rgmii2_txclko]
set_property PACKAGE_PIN T1 [get_ports {rgmii2_txdo[0]}]
set_property PACKAGE_PIN R2 [get_ports {rgmii2_txdo[1]}]
set_property PACKAGE_PIN R3 [get_ports {rgmii2_txdo[2]}]

set_property PACKAGE_PIN AB5 [get_ports rgmii3_rxctrli]
set_property PACKAGE_PIN AA5 [get_ports {rgmii3_rxdi[0]}]
set_property PACKAGE_PIN AB6 [get_ports {rgmii3_rxdi[1]}]
set_property PACKAGE_PIN AA6 [get_ports {rgmii3_rxdi[2]}]
set_property PACKAGE_PIN AB7 [get_ports {rgmii3_rxdi[3]}]
set_property PACKAGE_PIN Y3 [get_ports rgmii3_txctrlo]
set_property PACKAGE_PIN Y4 [get_ports rgmii3_txclko]
set_property PACKAGE_PIN AB3 [get_ports {rgmii3_txdo[0]}]
set_property PACKAGE_PIN AA3 [get_ports {rgmii3_txdo[1]}]
set_property PACKAGE_PIN AB2 [get_ports {rgmii3_txdo[2]}]
set_property PACKAGE_PIN AB1 [get_ports {rgmii3_txdo[3]}]




set_property PACKAGE_PIN T18 [get_ports {e1_pi[0]}]
set_property PACKAGE_PIN U18 [get_ports {e1_pi[1]}]
set_property PACKAGE_PIN AA19 [get_ports {e1_pi[2]}]
set_property PACKAGE_PIN AA18 [get_ports {e1_pi[3]}]
set_property PACKAGE_PIN U20 [get_ports {e1_pi[4]}]
set_property PACKAGE_PIN J15 [get_ports {e1_pi[5]}]
set_property PACKAGE_PIN F19 [get_ports {e1_pi[6]}]
set_property PACKAGE_PIN G20 [get_ports {e1_pi[7]}]

#set_property PACKAGE_PIN B22 [get_ports {e1_pi[8]}]
#set_property PACKAGE_PIN A21 [get_ports {e1_pi[9]}]

set_property PACKAGE_PIN N19 [get_ports {e1_pi[10]}]
set_property PACKAGE_PIN G16 [get_ports {e1_pi[11]}]
set_property PACKAGE_PIN D16 [get_ports {e1_pi[12]}]
set_property PACKAGE_PIN F16 [get_ports {e1_pi[13]}]
set_property PACKAGE_PIN J20 [get_ports {e1_pi[14]}]
set_property PACKAGE_PIN F15 [get_ports {e1_pi[15]}]

set_property PACKAGE_PIN U17 [get_ports {e1_ni[0]}]
set_property PACKAGE_PIN W17 [get_ports {e1_ni[1]}]
set_property PACKAGE_PIN AB18 [get_ports {e1_ni[2]}]
set_property PACKAGE_PIN V18 [get_ports {e1_ni[3]}]
set_property PACKAGE_PIN U22 [get_ports {e1_ni[4]}]
set_property PACKAGE_PIN J19 [get_ports {e1_ni[5]}]
set_property PACKAGE_PIN K16 [get_ports {e1_ni[6]}]
set_property PACKAGE_PIN F18 [get_ports {e1_ni[7]}]
set_property PACKAGE_PIN M21 [get_ports {e1_ni[8]}]
set_property PACKAGE_PIN L16 [get_ports {e1_ni[9]}]
set_property PACKAGE_PIN C13 [get_ports {e1_ni[10]}]
set_property PACKAGE_PIN J16 [get_ports {e1_ni[11]}]
set_property PACKAGE_PIN E16 [get_ports {e1_ni[12]}]
set_property PACKAGE_PIN P14 [get_ports {e1_ni[13]}]
set_property PACKAGE_PIN K19 [get_ports {e1_ni[14]}]
set_property PACKAGE_PIN K21 [get_ports {e1_ni[15]}]

set_property PACKAGE_PIN AA20 [get_ports {e1_po[0]}]
set_property PACKAGE_PIN AA21 [get_ports {e1_po[1]}]
set_property PACKAGE_PIN AB22 [get_ports {e1_po[2]}]
set_property PACKAGE_PIN Y21 [get_ports {e1_po[3]}]
set_property PACKAGE_PIN V22 [get_ports {e1_po[4]}]

#set_property PACKAGE_PIN J19 [get_ports {e1_po[5]}]

set_property PACKAGE_PIN L15 [get_ports {e1_po[6]}]
set_property PACKAGE_PIN H18 [get_ports {e1_po[7]}]
set_property PACKAGE_PIN G18 [get_ports {e1_po[8]}]
set_property PACKAGE_PIN K18 [get_ports {e1_po[9]}]
set_property PACKAGE_PIN G17 [get_ports {e1_po[10]}]
set_property PACKAGE_PIN J17 [get_ports {e1_po[11]}]
set_property PACKAGE_PIN T20 [get_ports {e1_po[12]}]

#set_property PACKAGE_PIN B17 [get_ports {e1_po[13]}]

set_property PACKAGE_PIN D17 [get_ports {e1_po[14]}]
set_property PACKAGE_PIN M13 [get_ports {e1_po[15]}]

set_property PACKAGE_PIN Y18 [get_ports {e1_no[0]}]
set_property PACKAGE_PIN AB20 [get_ports {e1_no[1]}]
set_property PACKAGE_PIN AB21 [get_ports {e1_no[2]}]
set_property PACKAGE_PIN W20 [get_ports {e1_no[3]}]
set_property PACKAGE_PIN U21 [get_ports {e1_no[4]}]
set_property PACKAGE_PIN K17 [get_ports {e1_no[5]}]
set_property PACKAGE_PIN L18 [get_ports {e1_no[6]}]
set_property PACKAGE_PIN H19 [get_ports {e1_no[7]}]
set_property PACKAGE_PIN G15 [get_ports {e1_no[8]}]
set_property PACKAGE_PIN R21 [get_ports {e1_no[9]}]
set_property PACKAGE_PIN H15 [get_ports {e1_no[10]}]
set_property PACKAGE_PIN P19 [get_ports {e1_no[11]}]
set_property PACKAGE_PIN E18 [get_ports {e1_no[12]}]
set_property PACKAGE_PIN C17 [get_ports {e1_no[13]}]
set_property PACKAGE_PIN E17 [get_ports {e1_no[14]}]
set_property PACKAGE_PIN M18 [get_ports {e1_no[15]}]

set_property PACKAGE_PIN N20 [get_ports stbus_clko]
set_property PACKAGE_PIN K13 [get_ports stbus_synco]
set_property PACKAGE_PIN M20 [get_ports stbus_di]
set_property PACKAGE_PIN N18 [get_ports stbus_do]
set_property PACKAGE_PIN M15 [get_ports stbus_sigi]
set_property PACKAGE_PIN M16 [get_ports stbus_sigo]

set_property PACKAGE_PIN R14 [get_ports {urxdi[0]}]
set_property PACKAGE_PIN P17 [get_ports {utxdo[0]}]
set_property PACKAGE_PIN R18 [get_ports {utxdo[1]}]
set_property PACKAGE_PIN N17 [get_ports {urxdi[1]}]
set_property PACKAGE_PIN N15 [get_ports {swi[3]}]
set_property PACKAGE_PIN R17 [get_ports {swi[1]}]
set_property PACKAGE_PIN P16 [get_ports {swi[0]}]
set_property PACKAGE_PIN N14 [get_ports {swi[2]}]
#set_property PACKAGE_PIN N13 [get_ports hooki]
#set_property PACKAGE_PIN R16 [get_ports ringo]
#set_property PACKAGE_PIN P15 [get_ports phone_ledo]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk65mi_IBUF]
##########################################################
# The RGMII receive interface requirement allows a 1ns setup and 1ns hold - this is met but only just so constraints are relaxed
#create_clock -period 8.000 -name rgc0 [get_ports rgmii0_rxclki]
#set_input_delay -clock [get_clocks {rgc0}] -max -1.5 [get_ports {rgmii0_rxd[*] rgmii0_rx_ctl}]
#set_input_delay -clock [get_clocks {rgc0}] -min -2.8 [get_ports {rgmii0_rxd[*] rgmii0_rx_ctl}]
#set_input_delay -clock [get_clocks {rgc0}] -clock_fall -max -1.5 -add_delay [get_ports {rgmii0_rxd[*] rgmii0_rx_ctl}]
#set_input_delay -clock [get_clocks {rgc0}] -clock_fall -min -2.8 -add_delay [get_ports {rgmii0_rxd[*] rgmii0_rx_ctl}]


set_clock_groups -asynchronous -group {[get_clocks ref_clk125m_pi]}
set_clock_groups -asynchronous -group {[get_clocks clk65mi]}
set_clock_groups -asynchronous -group {[get_nets spi_clki_IBUF]}
set_clock_groups -asynchronous -group {[get_ports clk125m_syni]}

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets spi_clki_IBUF]

create_clock -period 8.000 -name clk125m_syni -waveform {0.000 4.000} [get_ports clk125m_syni]
create_clock -period 15.385 -name clk65mi -waveform {0.000 7.693} [get_ports clk65mi]
create_clock -period 8.000 -name ref_clk125m_pi -waveform {0.000 4.000} [get_ports ref_clk125m_pi]
create_clock -period 1000.000 -name spi_clki -waveform {0.000 500.000} [get_ports spi_clki]



create_clock -period 8.000 -name clk125m_syni -waveform {0.000 4.000} [get_ports clk125m_syni]
create_clock -period 15.385 -name clk65mi -waveform {0.000 7.693} [get_ports clk65mi]
create_clock -period 8.000 -name ref_clk125m_pi -waveform {0.000 4.000} [get_ports ref_clk125m_pi]
create_clock -period 1000.000 -name spi_clki -waveform {0.000 500.000} [get_ports spi_clki]
create_clock -period 10.000 -name VIRTUAL_clk_out1_pll125_100 -waveform {0.000 5.000}
set_input_delay -clock [get_clocks clk65mi] -min -add_delay 2.000 [get_ports {e1_ni[*]}]
set_input_delay -clock [get_clocks clk65mi] -max -add_delay 6.000 [get_ports {e1_ni[*]}]
set_input_delay -clock [get_clocks clk65mi] -min -add_delay 2.000 [get_ports {e1_pi[*]}]
set_input_delay -clock [get_clocks clk65mi] -max -add_delay 6.000 [get_ports {e1_pi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports {rmii0_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports {rmii0_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports {rmii0_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports {rmii0_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports {rmii1_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports {rmii1_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports {rmii1_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports {rmii1_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports {rmii2_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports {rmii2_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports {rmii2_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports {rmii2_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports {rmii3_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports {rmii3_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports {rmii3_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports {rmii3_rxdi[*]}]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports rmii0_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports rmii0_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports rmii0_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports rmii0_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports rmii1_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports rmii1_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports rmii1_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports rmii1_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports rmii2_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports rmii2_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports rmii2_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports rmii2_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -min -add_delay 2.000 [get_ports rmii3_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -clock_fall -max -add_delay 3.000 [get_ports rmii3_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -min -add_delay 2.000 [get_ports rmii3_rxdvi]
set_input_delay -clock [get_clocks VIRTUAL_clk_out1_pll125_100] -max -add_delay 3.000 [get_ports rmii3_rxdvi]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports {rgmii0_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports {rgmii0_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports {rgmii0_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports {rgmii0_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports {rgmii1_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports {rgmii1_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports {rgmii1_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports {rgmii1_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports {rgmii2_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports {rgmii2_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports {rgmii2_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports {rgmii2_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports {rgmii3_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports {rgmii3_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports {rgmii3_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports {rgmii3_txdo[*]}]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports rgmii0_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports rgmii0_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports rgmii0_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports rgmii0_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports rgmii1_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports rgmii1_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports rgmii1_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports rgmii1_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports rgmii2_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports rgmii2_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports rgmii2_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports rgmii2_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -min -add_delay -2.000 [get_ports rgmii3_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -clock_fall -max -add_delay 2.000 [get_ports rgmii3_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -min -add_delay -2.000 [get_ports rgmii3_txctrlo]
set_output_delay -clock [get_clocks ref_clk125m_pi] -max -add_delay 2.000 [get_ports rgmii3_txctrlo]
set_clock_groups -asynchronous -group [get_clocks clk65mi] -group [get_clocks clkout0]
set_clock_groups -asynchronous -group [get_clocks clk65mi] -group [get_clocks clkout0_1]
set_false_path -from [get_clocks clk65mi] -to [get_clocks ref_clk125m_pi]
set_false_path -from [get_clocks clk65mi] -to [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins u_mac/tri_mode_ethernet_mac_support_clocking_i/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks ref_clk125m_pi] -to [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks ref_clk125m_pi] -to [get_clocks -of_objects [get_pins u_pll125_100/inst/plle2_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins u_pll125_100/inst/plle2_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins u_pll125_100/inst/plle2_adv_inst/CLKOUT0]] -to [get_clocks ref_clk125m_pi]
set_false_path -from [get_clocks clk65mi] -to [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/rxoutclk_mmcm1_i/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks clk65mi] -to [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks clk65mi] -to [get_clocks ref_clk125m_pi]
set_false_path -from [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0]] -to [get_clocks ref_clk125m_pi]
set_false_path -from [get_clocks -of_objects [get_pins u_line/line2_3125_support_i/gt_usrclk_source/txoutclk_mmcm0_i/mmcm_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins u_pll125_100/inst/plle2_adv_inst/CLKOUT0]]

set_false_path -from [get_clocks clk125m_syni] -to [get_clocks clk65mi]
set_false_path -from [get_clocks clk_out1_pll78_25_2] -to [get_clocks clk65mi]
set_false_path -from [get_clocks ref_clk125m_pi] -to [get_clocks clk65mi]
set_false_path -from [get_clocks clk65mi] -to [get_clocks clk_out1_pll78_25_3]
set_false_path -from [get_clocks spi_clki] -to [get_clocks ref_clk125m_pi]
set_false_path -from [get_clocks clkout0_1] -to [get_clocks clkout0]

set_false_path -from [get_clocks clkout0] -to [get_clocks clkout0_1]
set_false_path -from [get_clocks clk125m_syni] -to [get_clocks clk_out1_pll125_100]
set_false_path -from [get_clocks clk125m_syni] -to [get_clocks clk_out1_pll78_25_2]
set_false_path -from [get_clocks clk125m_syni] -to [get_clocks clk_out1_pll78_25_3]
set_false_path -from [get_clocks clk125m_syni] -to [get_clocks clkout0_2]

set_false_path -from [get_clocks clk125m_syni] -to [get_clocks clkout0_1]
set_false_path -from [get_clocks clk125m_syni] -to [get_clocks clkout0]


set_property PACKAGE_PIN H4 [get_ports rgmii0_rxclki]
set_property PACKAGE_PIN L3 [get_ports rgmii1_rxclki]
set_property PACKAGE_PIN V4 [get_ports rgmii2_rxclki]
set_property PACKAGE_PIN T5 [get_ports rgmii3_rxclki]
set_property PACKAGE_PIN R4 [get_ports {rgmii2_txdo[3]}]

set_property PACKAGE_PIN G13 [get_ports {e1_pi[9]}]
set_property PACKAGE_PIN J14 [get_ports {e1_pi[8]}]
set_property PACKAGE_PIN H14 [get_ports {e1_po[5]}]
set_property PACKAGE_PIN L13 [get_ports {e1_po[13]}]
set_property PACKAGE_PIN G1 [get_ports {rgmii0_rxdi[3]}]
set_property PACKAGE_PIN F4 [get_ports {rgmii0_txdo[3]}]
